1. Field of Use
The present invention relates to the testing of data processing systems and more particularly to the testing of cache systems.
2. Prior Art
It is well known in the art to provide cache units between a central processing unit (CPU) and a main store to improve overall system performance. However, since the cache unit is normally invisible to the operating system software during normal operation, errors or faults occurring within the cache unit are not detectable by such software. That is, when the cache is unable to provide correct data in response to a CPU request, the cache unit fetches the data from main store. This results in decreased system performance.
In view of the above, it becomes difficult to diagnose whether or not the cache unit is operating properly. In the past elaborate software diagnostic routines were employed for testing cache operation which involved transferring information from main store to cache for comparison with such known information when read from cache.
In order to eliminate the need for such elaborate software, one system arrangement enables the cache unit to be placed in a test and verification mode of operation wherein hardware faults can be signalled to the CPU. This arrangement is described in U.S. Pat. No. 4,190,885, issued Feb. 26, 1980, and is assigned to the same assignee as named herein. In greater detail, this system employs test and verification apparatus which responds to certain commands which enable the cache system to signal when the data requested from cache is not stored in cache after the cache has been initialized. This enables the test and diagnostic apparatus to test the directory and associated logic circuits. In this type of system, the cache is bypassed upon the detection of fault conditions by the CPU.
To improve the reliability of such cache systems, the cache system of the first related patent application includes control apparatus which couples to round robin replacement apparatus which is used to identify the cache level into which information is to be written. The control apparatus combines error signals from error checking circuits with signals indicative of cache hits to produce invalid hit signals. These signals condition the replacement apparatus, in addition to other portions of the cache system, to degrade cache operation to those levels detected as being free from errors. While the cache arrangement improves system reliability and performance, it makes diagnosis of faults more difficult.
The second related patent application discloses a cache unit which includes test mode logic circuits for enabling the cache memory section without controller interference. While the arrangement permits direct testing of the cache memory, it does not enable testing of the controller cache sections. Also, since the arrangement has particular application in factory test environment, it cannot be easily adapted for use with standard test and verification procedures carried out under the control of the system's central processing unit.
Accordingly, it is a primary object of the present invention to provide testing apparatus which facilitates the detection of faults within a cache unit during test and verification operations.
It is a further object of the present invention to provide testing apparatus which facilitates the detection of faults within the controller portions of a cache unit.
It is still a further object of the present invention to provide apparatus for testing the control circuits of a multilevel cache unit which is automatically degradable.